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[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 1 - 1. general description the ak553 x series is a 32 - bit, 768 khz sampling, differential input a/d converter for digital audio systems. it achieves 111 db dynamic range and 1 03 db s / (n+d) while maintaining low power consumption performance. the ak553 8 in tegrates a 8 - channel a/d converter, suitable for mixers and multi - channel recorders. four types of digital filters are integrated and selectable according to the sound quality preference . the ak553 8 can be easily connected to a dsp by supporting tdm audio formats. additionally, it supports dsd output up to 11.2mhz. the channel summation improves the dynamic range to 114 db in 8 - to - 4 mode , to 117 db in 8 - to - 2 mode and to 120 db in 8 - to - 1 mode. 2. features ? sampling rate: 8 khz - 768 khz ? input: full differential inputs ? s/(n+d): 1 0 3 db ? dr: 1 1 1 db ( 8 - to - 4 mode : 1 1 4 db , 8 - to - 2 mode : 1 17 db, 8 - to - 1 mode : 1 2 0 db) ? s/n: 1 11 db (8 - to - 4 mode: 114 db, 8 - to - 2 mode: 117 db, 8 - to - 1 mode: 120 db) ? internal filter: four types of lpf, digital hpf ? power supply : 3.0 - 3.6 v ( analog ), 1.7 - 1.98 v or 3.0 - 3.6 v ( digital ) ? output format : pcm mode: 24/32 - bit msb justified , i 2 s or tdm dsd mode: dsd native 64, 128, 256 maximized slot efficiency in tdm mode by optimal data placed mode ? cascade tdm i/f: tdm51 2 : fs= 48 kh z tdm256: fs = 96 khz or 48 khz tdm128: fs= 192 khz , 96 khz or 48 khz ? operation mode: master mode & slave mode ? detection function: input overflow flag ? serial interface: 3 - wire serial and i 2 c p i/f (pin setting is also available) ? power consumption : 182 mw (@ avdd= 3.3 v, tvdd= 3.3 v, fs= 48 khz) ? package : 64 - pin qfn 8 - channel differential 32 - bit ? ? adc ak553 8
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ............................ 1 2. features ................................ ................................ ................................ ................................ .............. 1 3. table of contents ................................ ................................ ................................ ................................ 2 4. block diagram ................................ ................................ ................................ ................................ ..... 3 block diagram ................................ ................................ ................................ ................................ .... 3 5. pin configurations and functions ................................ ................................ ................................ ...... 4 pin configurations ................................ ................................ ................................ ............................. 4 pin functions ................................ ................................ ................................ ................................ ..... 5 handling of unused pin ................................ ................................ ................................ ..................... 7 6. absolute maximum ratings ................................ ................................ ................................ ................ 8 7. recommended operation conditions ................................ ................................ ................................ 8 8. analog characteristics ................................ ................................ ................................ ........................ 9 9. filter characteristics ................................ ................................ ................................ ......................... 10 adc filter characteristics (fs= 48 khz) ................................ ................................ .......................... 10 adc filter characteristics (fs= 96 khz) ................................ ................................ .......................... 12 adc filter characteristics (fs= 192 khz) ................................ ................................ ........................ 14 adc filter characteristics (fs= 384 khz) ................................ ................................ ........................ 16 adc filter characteristics (fs= 768 khz) ................................ ................................ ........................ 17 10. dc characteristics ................................ ................................ ................................ ............................ 18 11. switching characteristics ................................ ................................ ................................ .................. 19 timing diagram ................................ ................................ ................................ ............................... 26 12. functional descriptions ................................ ................................ ................................ .................... 31 digital core power supply ................................ ................................ ................................ ............... 31 output mode ................................ ................................ ................................ ................................ .... 31 master mode and slave mode ................................ ................................ ................................ ......... 31 system clock ................................ ................................ ................................ ................................ ... 31 audio inte rface format ................................ ................................ ................................ .................... 34 channel summation (pcm mode, dsd mode) ................................ ................................ .............. 46 optimal data placement (pcm mode, dsd mode) ................................ ................................ ........ 46 ch power down & channel summation setting (pcm mode, dsd mode) ................................ .. 47 digital filter setting (pcm mode) ................................ ................................ ................................ .... 53 digital hpf (pcm mode) ................................ ................................ ................................ ................. 53 overflow detection (pcm mode, dsd mode) ................................ ................................ ................. 53 ldo ................................ ................................ ................................ ................................ .................. 54 reset ................................ ................................ ................................ ................................ ................ 54 power up/down sequence ................................ ................................ ................................ ............. 55 operation mode control ................................ ................................ ................................ .................. 58 register control interface ................................ ................................ ................................ ................ 58 register map ................................ ................................ ................................ ................................ .... 62 register definitions ................................ ................................ ................................ .......................... 62 13. recommended external circuits ................................ ................................ ................................ ...... 65 14. package ................................ ................................ ................................ ................................ ............ 68 outline dimension s ................................ ................................ ................................ .......................... 68 material & lead finish ................................ ................................ ................................ ..................... 68 marking ................................ ................................ ................................ ................................ ............ 68 15. ordering guide ................................ ................................ ................................ ................................ . 69 16. revision history ................................ ................................ ................................ ................................ 69 important notice ................................ ................................ ................................ ........................... 70
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 3 - 4. block diagram block diagram figure 1 . block diagram voltage reference serial output interface delta - sigma modulator controller ldo decimation filter hpf ain1p ain1n dif0/dsdsel0 dif1/dsdsel1 bick/dclk lrck/dsdol1 psn/c ad0_spi cks0/sda/cdti cks1/cad0_i2c/csn cks2/scl/cclk cks3/cad1 vdd18 vrefh1 vrefl1 vrefh2 vrefl2 vrefh3 vrefl3 vrefh4 vrefl4 ldoe tvdd avdd1 avss1 avdd2 avss2 dvss pdn delta - sigma modulator decimation filter hpf ain2p ain2n delta - sigma modulator decimation filter hpf ain3p ain3n delta - sigma modulator decimation filter hpf ain 4p ain4n delta - sigma modulator decimation filter hpf ain5p ain5n delta - sigma modulator decimation filter hpf ain6p ain6n delta - sigma modulator decimation filter hpf ain7p ain7n delta - sigma modulator decimation filter hpf ain8p ain8n tdmin/ dsdor1 sdto1/dsdol2 sdto2/dsdor2 sdto3/dsdol3 sdto4/dsdor3 dsdol4 dsdor4 dp tdm0 tdm1 odp mclk test slow/dckb sd/pmod pw2 pw1 pw0 msn ovf dcks/hpfe i2c
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 4 - 5. pin configurations and functions pin configurations figure 2 . pin configurations dif0/dsdsel0 dif1/dsdsel1 tdm0 tdm 1 psn/cad 0_spi i2c dp dcks/ hpfe ldoe odp ain1p ain1n vrefl 1 vrefh1 ain2n ain2p msn pw2 pw1 pw0 pdn vdd18 dvss tvdd mclk test ain8p ain8n vrefl4 vrefh4 ain7n ain7p avss1 avdd1 ain3p ain3n vrefl2 vrefh2 ain4n ain4p ain5p ain5n vrefh3 vrefl3 ain6n ain6p avdd2 avss2 sd/pmod slow/dckb cks3/cad1 cks2/scl/cclk cks1/cad0_i2c/csn cks0/sda/cdti ovf dsdor4 dsdol4 sdto4/dsdor3 sdto3/dsdol3 sdto2/dsdor2 sdto1/dsdo l2 tdmin/dsdor1 lrck/dsdol1 bick/dclk 64qfn top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 4 6 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 exposed pad (back face) * * the exposed pad at back face of the package must be open or connected to the ground of the board .
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 5 - pin functions no. pin name i/o function power down status 1 avss1 - analog ground pin(ain1 - 4) - 2 avdd1 - analog power supply pin (ain1 - 4) , 3.0 - 3.6 v - 3 ain3p i channel 3 positive input pin - 4 ain3n i channel 3 negative input pin - 5 vrefl2 i adc low level voltage reference input pin - 6 vrefh 2 i adc high level voltage reference input pin - 7 ain4n i channel 4 negative input pin - 8 ain4p i channel 4 positive input pin - 9 ain5p i channel 5 positive input pin - 10 ain5n i channel 5 negative input pin - 11 vrefh3 i adc high level voltage re ference input pin - 12 vrefl3 i adc low level voltage reference input pin - 13 ain6n i channel 6 negative input pin - 14 ain6p i channel 6 positive input pin - 15 avdd2 - analog power supply pin (ain5 - 8) , 3.0 - 3.6 v - 16 avss2 - analog ground pin(ain5 - 8 ) - 17 ain7p i channel 7 positive input pin - 18 ain7n i channel 7 negative input pin - 19 vrefh4 i adc high level voltage reference input pin - 20 vrefl4 i adc low level voltage reference input pin - 21 ain8n i channel 8 negative input pin - 22 ain8 p i channel 8 positive input pin - 23 test i test enable pin . this pin is pull down by 100k ? internally - 24 mclk i master clock input pin - 25 tvdd - digital i/o buffers and ldo power supply pin 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ). - 26 dvss - digital ground pin - 27 vdd18 i digital core power supply pin, 1.7 - 1.98 v (ldoe pin= l ) - o ldo stabilization capacitor c o nnect pin. (ldoe pin= h ) hi - z & pull down with 500 ? 28 pdn i reset & power down pin l : reset & power down, h : normal operation - 29 pw0 i power management pin, channel summation select pin - 30 pw1 i power management pin, channel summation select pin - 31 pw2 i power management pin, channel summation select pin - 32 msn i master/slave select pin l : s lave mode, h : master mode - 33 bick i audio serial data clock input pin in pcm & slave mode . this pin is pulled down by 100 k ? internally - o audio serial data clock output pin in pcm & master mode this pin is pulled down by 100 k ? internally hi - z dclk o dsd clock output pin in dsd mode this pin is pulled down by 100 k ? internally hi - z 34 lrck i channel clock input pin in pcm & slave mode this pin is pulled down by 100 k ? internally - o channel clock output pin in pcm & master mode this pin is pulled down by 100 k ? internally hi - z dsdol1 o audio serial data output pin for ain1 in dsd mode this pin is pulled down by 100 k ? internally hi - z
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 6 - no. pin name i/o function power down status 35 tdmin i tdm data input pin in pcm mode this pin is pulled down by 100 k ? ? 2 c bus s erial c ontrol m ode hi - z cdti i control data input pin in 3 - wire s erial c ontrol m ode - 44 cks1 i clock mode select pin - cad0_i2c i chip address 0 pin in i 2 c bus s erial c ontrol m ode - csn i chip select pin in 3 - wire s erial c ontrol m ode - 45 cks2 i clock mode select pin - scl i control data clock pin in i 2 c bus s erial c ontrol m ode - cclk i control data clock pin in 3 - wire s erial c ontrol m ode - 46 cks3 i clock mode select pin - cad1 i chip address 1 pin in i 2 c bus or 3 - wire s erial c ontrol m ode - 47 slow i slow roll - off digital filter select pin in pcm mode - dckb i polarity of dclk pin in dsd mode - 48 sd i short delay digital filter select pin in pcm mode - pmod i dsd phase modulation mode s elect pin in dsd mode - 49 dif0 i audio data format select pin in pcm mode 2 s - dsdsel0 i dsd sampling rate control pin in dsd mode - 50 dif1 i audio data format select pin in pcm mode this pin must be fixed to l when using dsd mode. this pin must be fixed to l when using dsd mode. 2 c bus serial control mode, l: 3 h: i 2 c bu s serial c ontrol m ode or parallel control mode - 55 dp i dsd mode enable pin
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 7 - no. pin name i/o function power down status 56 hpfe i high pass filter enable pin ? handling of unused pin the unused i/o pins should be connected appropriately. 1. pcm mode classification pin name setting analog ain1 - 8p, ain1 - 8n open vrefh1 - 4 connect to avdd vrefl1 - 4 connect to avss digital tdmin, test connect to dvss sdto1 - 4, dsdol4, dsdor4, ovf open 2. dsd mode classification pin name setting analog ain1 - 8p, ain1 - 8n open vrefh1 - 4 connect to avdd vrefl1 - 4 connect to avss digital tdm0, tdm1, test connect to dvss dsdol1 - 4, dsdor1 - 4, ovf open note 2 . unused channels must be powered down.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 8 - 6. absolute maximum ratings (vss= 0 v ; note 3 ) parameter symbol m in . m ax . unit power supplies : analog (avdd pin) digita l interface (tvdd pin) digital core (vdd18 pin) ( note 4 ) avdd am tvdd am vdd18 am ? ? ? ? ? ? ? ? ? v ldo is off (ldoe pin = l) and an external power is supplied to the vdd18 pin. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extrem es. 7. recommended operation conditions ( vss= 0 v ; note 3 ) parameter symbol m in . t yp . m ax . unit power supplies analog (avdd pin) avdd 3.0 3.3 3.6 v (ldoe pin= l) h) h voltage reference l voltage reference pin = l. the power up sequence between avdd pin and tvdd pin or between avdd pin and vdd18 pin is not critical. note 6 . tvdd must not exceed vdd18 0.1 v when ldoe pin= l. note 7 . when ldoe pin = h, the internal ldo supplies 1.8 v (typ). the power up sequences between avdd pin and tvdd pin is not critical. note 8 . vrefh1 - 4 must not exceed avdd+0.1 v. note 9 . vrefl1 - 4 must be connected to avss. analog input voltage is proportional to {(vrefh) C (vrefl)}. vin (typ, @ 0db) = ? 1.85 ? {(vrefh) C (vrefl)} / 3.3 [v]. * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 9 - 8. analog characteristics (ta= 25 ? c ; avdd = 3.3 v ; t v d d= 3.3 v, fs= 48 khz, bick = 64fs; signal freq uency= 1 khz; 24 - bit data; measurement frequency= 20 hz - 20 khz at fs= 48 khz, 40 hz - 40 khz at fs= 96 khz , 4 0 hz - 4 0 khz at fs= 192 khz , unless otherwise specified. ) parameter m in . t yp . m ax . unit analog input characteristics: resolution - - 32 bit input voltage ( note 10 ) ? ? ? ? ? ? ? ? ? ? ? ? ? 8.8 10.4 12.0 k ? ? ? ? ? power supplies power supply current normal operation ( pdn pin = ? ? (ainnn) that the adc output becomes full - scale (n=1 - 8 ). vin = 0.56 ? ( vref h m ? vrefl m ) [vpp] . (m=1 - 4) note 11 . psrr is applied to avd d, tvdd with 1 khz, 20 mvpp sine wave. the vrefh1 - 4 are held to the fixed voltage. note 12 . all digital inputs are fixed to tvdd or tvss.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 10 - 9. filter characteristics adc filter characteristics (fs= 48 khz) (ta= ? 40 - + 10 5 ? c; avdd = 3.0 - 3.6 v, tvdd= 1.7 - 1.98 v (ldoe pin = l ) or 3.0 - 3.6 v (ldoe pin = h ) , vdd18= 1. 7 - 1.98 v (ldoe pin= l ) ) parameter symbol m in . t yp . m ax . unit digital filter (decimation lpf): sharp roll - o ff ( figure 3 ) ( sd pin = passband ( note 13 ) +0.0 01 / ? ? ? digital filter (decimation lpf): slow roll - off ( figure 4 ) ( sd pin= +0.001/ ? ? pb 0 - - 21. 9 12.5 - khz khz stopband ( note 13 ) sb 36.5 - - khz stopband attenuation sa 85 - - db group delay distortion 0 - 20.0 khz ? digital filter (decimation lpf): short delay sharp roll - off filter ( figure 5 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): short delay slow roll - off ( figure 6 ) ( sd pin= +0.001/ ? ? pb 0 - - 21. 9 12.5 - khz khz stopband ( note 13 ) sb 36.5 - - khz stopband attenuation sa 85 - - db group delay distortion 0 - 20.0 khz ? digital filter (hpf): frequency response ? ? ? ? 0. 06 db) = 0.46 ? fs (sharp roll - off). for e xample, pb ( +0.001 db / ? 0.0 76 db) = 0.26 ? fs (slow roll - off). note 14 . the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the l channel msb output timing of the sdto. it may have an error of +1[1/fs ] at maximum when outputting data via audio interfaces.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 11 - figure 3 . sharp roll - off (fs= 48 khz) figure 4 . slow roll - off (fs= 48 khz) figure 5 . short delay sharp roll - off (fs= 48 khz) figure 6 . short delay slow roll - off (fs= 48 khz)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 12 - adc filter characteristics (fs= 96 khz) ( ta= ? 40 - + 10 5 ? c; avdd= 3.0 - 3.6 v, tvdd=1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin= l ) ) parameter symbol mi n . t yp . m ax . unit digital filter (decimation lpf): sharp roll - off ( figure 7 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): slow roll - off ( figure 8 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): short delay sharp roll - off ( figure 9 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): short delay slow roll - off ( figure 10 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (hpf): frequency response ? ? ? ? 0.06 db) = 0.46 ? fs (sharp roll - off). for example, pb ( +0.001 db/ ? 0.07 6 db) = 0.26 ? fs (slow roll - off). note 14 . the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the l channel msb output timing of the sdto. it may have an error of +1[1/fs ] at maximum when outputting data via audio interfaces.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 13 - figure 7 . sharp roll - off (fs= 96 khz) figure 8 . slow roll - off (fs= 96 khz) figure 9 . short delay sharp roll - off (fs= 96 khz) figure 10 . short delay slow roll - off (fs= 96 khz)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 14 - adc filter characteristics (fs= 192 khz) ( ta= ? 40 - + 10 5 ? c; avdd= 3.0 - 3.6 v, tvdd=1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin= l ) ) parameter symbol m in . t yp . m ax . unit digital filter (decimation lpf): sharp ro ll - off ( figure 11 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): slow roll - off ( figure 12 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): short delay sharp roll - off filter ( figure 13 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (decimation lpf): short delay slow roll - off filter ( figure 14 ) ( sd pin= passband ( note 13 ) +0.001 / ? ? ? digital filter (hpf): frequency response ? ? ? ? 0.0 37 db) = 0.4 3 6 ? fs (sharp roll - off). for e xam ple, pb ( +0.001 db/ ? 0. 1 db) = 0. 1 6 4 ? fs (slow roll - off). note 14 . the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the l channel msb output timing of the sdto. it may have an error of +1[1/fs ] at maximum when outputting data via audio interfaces.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 15 - figure 11 . sharp roll - off (fs= 192 khz) figure 12 . slow roll - off (f s= 192 khz) figure 13 . short delay sharp roll - off (fs= 192 khz) figure 14 . short delay slow roll - off (fs= 192 khz)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 16 - adc filter characteristics (fs= 384 khz) ( ta= ? 40 - + 10 5 ? c; avdd= 3.0 - 3.6 v, tvdd=1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin= l ) ) parameter symbol min. typ. max. unit digital filter (decimation lpf) ( figure 15 ) (sd pin = ? ? ? ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 17 - adc filter characteristics (fs= 768 khz) ( ta= ? 40 - + 10 5 ? c; avdd= 3.0 - 3.6 v, tvdd=1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin= l ) ) parameter symbol min. typ. max. unit digital filter (decimation lpf) ( figure 16 ) (sd pin = ? ? ? ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 18 - 10. dc characteristics (ta= ? 40 - 105 ? c; avdd= 3.0 - 3.6 v, vdd18= 1.7 - 1.98 v (ldoe pin=l)) parameter symbol m in . t yp . m ax . unit tvdd= 3.0 - 3.6 v (ldoe pin= ? ? ? ? ? ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 19 - 11. switching characteristics (ta= ? 40 - +105 ? c; avdd = 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin = l ) or 3.0 - 3.6 v (ldoe pin = h ), vdd18= 1. 7 - 1.98 v (ldoe pin= l) , c l = 1 0 pf ) parameter symbol m in . t yp . m ax . unit master clock (mclk)timing ( figure 17 , figure 18 ) frequency duty cycle fclk dclk 2.048 45 - - 49.152 55 mhz % lrck timing (slave m ode) ( figure 17 ) normal m ode (tdm1 - 0 bits = 00) frequency normal speed m ode double speed m ode quad speed m ode oct speed mode hex speed mode duty cycle fs fsn fsd fsq fso fsh duty 8 54 108 - - 45 - - - 384 768 - 5 4 108 216 - - 55 khz khz khz khz khz % tdm128 mode (tdm1 - 0 bits = 01) frequency normal speed m ode double speed m ode quad speed m ode high time low time fs fsn fsd fsq tlrh tlrl 8 54 108 1/128fs 1/128fs - - - - - 54 108 216 - - khz khz khz ns ns tdm256 mode (tdm1 - 0 bits = 10) frequency normal speed m ode double speed m ode high time low time fs fsn fsd tlrh tlrl 8 54 1/256fs 1/256fs - - - - 54 108 - - khz khz ns ns tdm512 mode (tdm1 - 0 bits = 11) frequency normal speed m ode high time low time fs fsn tlrh tlrl 8 1/512fs 1/512fs - - - 54 - - khz ns ns lrck timing (master m ode) ( figure 18 ) normal m ode (tdm1 - 0 bits = 00) frequency normal speed m ode double speed m ode quad speed m ode oct speed mode hex speed mode duty cycle fs fsn fsd fsq fso fsh duty 8 54 108 - - - - - - 384 768 50 54 108 216 - - - khz khz khz khz khz % tdm128 mode (tdm1 - 0 bits = 01) frequency normal speed m ode double speed m ode quad speed m o de high time fs fsn fsd fsq tlrh 8 54 108 - - - - 1/4fs 54 108 216 - khz khz khz ns tdm256 mode (tdm1 - 0 bits = 10) frequency normal speed m ode double speed m ode high time fs fsn fsd tlrh 8 54 - - - 1/8fs 54 108 - khz khz ns tdm512 mode (tdm1 - 0 bits = 11) frequency normal speed m ode high time fs fsn tlrh 8 - - 1/16fs 54 - khz ns note 18 . when the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the ak553 8 should be reset by the p dn pin or rstn bit.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 20 - (ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf) parameter symbol m in . t yp . m ax . unit audio interface timing (slave m ode) normal m ode (td m1 - 0 bits = 00) ? fs ? 216 khz) ( figure 19 ) (ldoe pin = bick period normal speed m ode double speed m ode quad speed m od e bick pulse width low bick pulse width high lrck edge to bick ( bick to lrck edge ( 2 s m ode) bick to normal m ode (tdm1 - 0 bits = 00 ) (8 khz khz fs khz fs 2 s m ode) bick normal m ode (tdm1 - 0 bits = 00 ) (fs = 384 khz, 768 khz) ( figure 20 ) bick period oct speed m ode hex speed m ode bick pulse width low bick pulse width high lrck ed ge to bick
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 21 - ( ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf ) parameter symbol m in . t yp . m ax . unit audio interface timing (slave m ode) ( figure 21 ) tdm128 m ode (tdm1 - 0 bits = 01 ) bick period normal speed m ode double speed m ode quad speed m ode bick pulse width low bick pulse width high lrck edge to bick tdm256 m ode (tdm1 - 0 bits = 10 ) bick period normal speed m ode double speed m ode bick pulse width low bick pulse width high lrck edge to bick tdm512 m ode (tdm1 - 0 bits = 11 ) bick period normal speed m ode bick pulse width low bick pulse width high lrck edge to bick note 18 . when the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the ak553 8 should be reset by the p dn pin or rstn bit. note 19 . bick ri sing edge must not occur at the same time as lrck edge.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 22 - ( ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf ) parameter sym bol m in . t yp . m ax . unit audio interface timing (master mode) ( figure 22 ) normal mode (tdm1 - 0 bits = 00) (8 khz ? ? bick to lrck edge bick to sdto1/2 ? ? normal mode (tdm1 - 0 bits = 00) (fs = 384khz, 768 khz) (ldoe pin = h) bick to lrck edge bick to sdto1/2 ? ? normal mode (tdm1 - 0 bits = 00) (fs = 384 khz ,768 khz) (ldoe pin = l) bick to lrck edge bick to sdto1/2 ? ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 23 - ( ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin = h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf ) parameter symbol m in . t yp . m ax . unit audio interface timing (master mode) ( figure 22 ) tdm128 mode (tdm1 - 0 bits = 01) bick period normal speed m ode doubl e speed m ode quad speed m ode bick duty bick to lrck edge bick to sdto1/2 tsdh tsds - - - - ? ? tdm256 mode (tdm1 - 0 bits = 10) bick period normal speed m ode double speed m ode bick duty bick to lrck edge bick to sdto1 tsdh tsds - - - ? ? tdm512 mode (tdm1 - 0 bits = 11) bick period normal speed m ode bick duty bick to lrck edge bick to sdto1 tsdh tsds - - ? ? note 18 . when the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the ak553 8 should be reset by the p dn pin or rstn bit.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 24 - ( ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3.0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf ) parameter symbol m in . t yp . m ax . unit audio interface timing (master m ode) ( figure 23 ) dsd audio interfac e timing (64 fs m ode, dsdsel 1 - 0 bits = 00 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsd o l/r ( note 20 ) tdck tdckl tdckh tddd - 144 144 ? dsd audio interface timing (128 fs m ode, dsdsel 1 - 0 bits = 01 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsd o l/r ( note 20 ) tdck tdckl tdckh tddd - 72 72 ? dsd audio interface timing (256 fs m ode, dsdsel 1 - 0 bit s = 1 0 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsd o l/r ( note 20 ) tdck tdckl tdckh tddd - 36 36 ? tddd is defined from a falling edge of dclk to a dsd o l/r edge when dckb bit = 0 and it is defined from a rising edge of dclk to a dsd o l/r edge when dckb bit = 1.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 25 - ( ta= ? 40 - +105 ? c; avdd= 3.0 - 3.6 v , tvdd= 1.7 - 1.98 v (ldoe pin= l ) or 3 .0 - 3.6 v (ldoe pin= h ), vdd18= 1.7 - 1.98 v (ldoe pin=l) , c l = 1 0 pf ) note 21 . data must be held for sufficient time to bridge the 300 ns transition time of scl. note 22 . the ak553 8 can be reset by setting the pdn pin to l upon power - up. the pdn pin must held l for more than 150 ns for a certain reset. the ak553 8 is not reset by the l pulse less than 30 ns. note 23 . this cycle is the number of lrck rising edges from the pdn pin = h. parameter symbol min. typ. max. unit control inte r face timing (3 - wire serial m ode): ( figure 25 ) ( figure 26 ) cclk period cclk pulse width low pulse width high cdti setup timing cdti hold timing csn control interface timing (i 2 c bus m ode) : ( figu re 27 ) scl clock frequency bus free time between transmissions start condition hold tune (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 21 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd sta tlow thigh tsu sta thd dat tsu dat tr tf tsu sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - - - - - - - - - - - - - - 400 - - - - - - - 1.0 0.3 - 50 400 khz s s s s s s s s s s ns pf power down & reset timing ( figure 28 ) pdn pulse width ( note 22 ) pdn reject pulse width ( note 22 ) pdn t tpd trpd tpdv 150 - - - - 583 - 30 - ns ns 1/fs
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 26 - timing diagram [1] pcm m ode figure 17 . clock timing (slave m ode) figure 18 . clock timing (master m ode) 1/fclk t d clkl t d clkh m clk tbck tbckl vih tbckh bick vil 1/fs lrck 50%tvdd tlrh tlrl duty =t lrh ? fs ? 100 or t lrl ? fs ? 100 50%tvdd dclk=tdclkh ? fs ? 100 or tdclkl ? fs ? 100 1/fclk tclkl tcl kh m clk t bck tbckl tbckh bick 5 0% t vd d 1/fs lrck 50% t vd d t lrh d uty=t lrh ? fs ? 100 dbck=t bckh / t bck ? 100 or t bckl / t bck ? 100 50%tvdd dclk=tclkh ? f clk ? 100 or tclkl ? f clk ? 100
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 27 - figure 19 . audio interface timing ( normal m ode & slave m ode : 8 khz fs 216 khz ) figure 20 . audio interface timing ( normal & slave m ode : fs=384 khz, 768 khz ) figure 21 . audio interface timing ( tdm & slave m ode) tlrb lrck vih bick vil tlrs sdto 1/2 /3/4 5 0% t vd d tbsd vih vil tblr tlrb lrck vih bick vil sdto 1/2 /3/4 5 0% t vd d vih vil tblr tbsdd tlrb lrck vih bick vil sdto 1 /2 /3/4 5 0% t vd d tbs dd vih vil tblr tsds t d m i n vih vil tsdh
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 28 - figure 22 . audio interface timing ( master m ode ) [2] dsd mode figure 23 . audio s erial interface timing (normal m ode, dckb bit= 0 or dckb pin= l ) figure 24 . audio serial inte rface timing (phase modulation m ode, dckb bit= 0 or dckb pin= l ) lrck bick sdto 1 /2 /3/4 tb sd tmblr 5 0% t v d d 5 0% t v d d 5 0% t v d d t d m i n tsdh tsds vih vil v o h dclk v o l tddd v o h dsd o l 1 - 4 dsd o r 1 - 4 v o l tdckh tdckl tdck v o h dclk v o l tddd v o h dsd o l 1 - 4 dsd o r 1 - 4 v o l tdckh tdckl tdck tddd
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 29 - [3] 3 - wire seri al interface figure 25 . write command input timing (3 - wire serial m ode) figure 26 . write data input timing (3 - wire serial m ode) [4]i 2 c interface figu re 27 . i 2 c bus m ode timing tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 30 - [5] power - d own timing figure 28 . power - down & reset timing vih vil 50%tvdd tpd sdto1/2/3/4 pd n tpdv trp d
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 31 - 12. functional descriptions digital core power s u pply the digital core of the ak553 8 is operates off of a 1.8 v power supply. normally, this voltage is generated by the internal ldo from tvdd (3.3 v) for digital interface . the internal ldo will be powered up by setting the ldoe pi n = h . set the ldoe pin to l and supply a 1.8 v power to the vdd18 pin externall y when a 1.8 v is used as tvdd. output mode the ak553 8 is able to output either pcm or dsd data. the dp pin or dp bit select the output mode. set the pw2 pin = pw1 pin = pw0 pin = l or rstn bit = 0 or pw 8 - 1 bits = 0h to reset all channels when changing the pcm/dsd mode. the ak553 8 outputs data from the sdto1 - 4 pins by bick and lrck in pcm mode. dsd data are output from the dsdol1 - 4 pins and dsdor1 - 4 pins by dclk i n dsd mode. dp pin d p bit interface l 0 pcm h 1 dsd table 1 pcm/dsd m ode control master mode and slave mode the ak553 8 requires a master clock (mclk), an audio serial data clock (bick) and an output channel clock (lrck) in pcm mode. in this case, the lrck frequency will be the sampling frequency. both master and slave modes are avail able in pcm mode. in master mode, the ak553 8 internally generates bick and lrck clocks from mclk inputs and outputs them from the bick pin and the lrck pin. in s lave mode , ak553 8 operates in the input mclk, bick and lrck . mclk must be synchronized with bic k and lrck but the phase is not important. the ak553 8 is in master mode when the msn pin = h and in slave mode when the msn pin = l. the ak553 8 requires a master clock (mclk) in dsd mode. slave mode is not available in dsd mode, only master mode is sup ported. system clock [1] pc m mode the external system clocks, which are required to operate the ak553 8 , are mclk, bick and lrck in pcm mode. mclk frequency is determined based on lrck frequency, according to the operation mode. table 2 , table 3 , table 4 show mclk frequencies correspond to the normal audio rate. set the frequency ratio between sampling frequency and mclk by the cks 3 - 0 pins ( table 5 ) all channels must be reset when changing the clock mode or audio interface format by the cks2 - 0 pins (bits), tdm1 - 0 pins (bits), dif1 - 0 pins (bits) and the msn pin. in parallel control mode, all channels will be reset by the pdn pin = l or pw2 - 0 pins = lll . in serial control mode, all channels will be reset by rstn bit = 0 or pw8 - 1 bits = 0h . a stable clock must be supplied after releasing the reset. the ak553 8 integrates a phase detec tion circuit for lrck. if the internal timing becomes out of synchronization in slave mode, the ak553 8 is reset automatically and the phase is resynchronized. the following sequence must be executed when synchronizing multiple ak553 8 s. stop all ak553 8 s in reset status by setting the pdn pin = l h after stopping the system clock. make pin or register settings while all channels are in reset status. after that, input the same system clock to all ak553 8 s.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 32 - f s mclk 32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 32 khz n/a n/a n/a n/a n/a n/a 8.192 mhz 12.288 mhz 16.384 mhz 24.576 mhz 32.768 mhz 48 khz n/a n/a n/a n/a n/a n/a 12.288 mhz 18.432 mhz 24.576 mhz 36.864 mhz n/a 96 khz n/a n/a n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n /a n/a 192 khz n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a 384 khz n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a n/a n/a 768 khz 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a n/a n/a n/a n/a (n/a: not a vailable) table 2 . system clock example (slave m ode) fs mclk 32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 32 khz n/a n/a n/a n/a n/a n/a 8.192 mhz 12.288 mhz 16.384 mhz 24.576 mhz 32.768 mhz 48 khz n/a n/a n/a n/a n/a n/a 12.288 mhz 18.432 mhz 24.576 mhz 36.864 mhz n/a 96 khz n/a n/a n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a 192 khz n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a 384 khz n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a n/a n/a 768 khz 24.576 mhz 36.864 mh z 49.152 mhz n/a n/a n/a n/a n/a n/a n/a n/a (n/a: not a vailable) table 3 . system clock example (master m ode) fs mclk 32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 32 khz n/a n/a n/a n/a n/a n/a n/a n/a 16.384 mhz 24.576 mhz 32.768 mhz 48 khz n/a n/a n/a n/a n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a 96 khz n/a n/a n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a 192 khz n/a n/a n/a n/a 24.576 mhz 36.864 mhz n/a n/a n/a n/a n/a 384 khz n/a n/a 24.576 mhz 36 .864 mhz n/a n/a n/a n/a n/a n/a n/a 768 khz 24.576 mhz 36.864 mhz na n/a n/a n/a n/a n/a n/a n/a n/a (n/a: not a vailable) table 4 . system clock example (auto m ode)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 33 - cks3 pin (bit) cks2 pin (bit) cks1 pin (bit) cks0 pin (bit) m s n p i n mclk frequency speed mode fs range l (0) l(0) l(0) l(0) l 128fs 24m quad speed 108 k hz ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 34 - [ 2 ] dsd mode the external clock, which is re quired to operate the ak553 8 , is mclk in dsd mode. t h e ak553 8 generates dclk from mclk inputs and dsd data outputs (dsdol1 - 4 and dsdor1 - 4 ) are synchronized with dclk. the necessary mclk frequencies are 512fs and 768fs (fs=32 khz, 44.1 khz, 48 khz). mclk fr equency can be changed by the dcks pin (bit). after exiting res et (pdn pin = l h) upon power - up, the ak553 8 is in power - down state until mclk is input. dcks pin (bit) mclk frequency (default) l ( 0 ) 512fs h ( 1 ) 768fs table 6 . system clock (dsd m ode) the ak553 8 supports 64fs, 128fs and 256fs dsd sampling frequencies (fs= 32 khz 44.1 khz, 48 khz). dsdsel1 - 0 pins (bits) control this setting ( table 7 ) . dsdsel1 pin (bit) dsdsel0 pin (bit) frequency mode dsd sampling frequency fs=32 khz fs =44.1 khz fs=48 khz l( 0 ) l( 0 ) 64fs 2.048 mhz 2.8224 mhz 3.072 mhz (default) l( 0 ) h( 1 ) 128fs 4.096 mhz 5.6448 mhz 6.144 mhz h( 1 ) l( 0 ) 256fs 8.192 mhz 11.2896 mhz 12.288 mhz h( 1 ) h( 1 ) - reserved reserved reserved table 7 . dsd sampling frequency s elect audio interface format tdm1 - 0 pins(bits), dif1 - 0 pins(bits ) , slow pin(bit) and sd pin(bit) settings should be changed when all channel are reset condition . [1] pcm m od e 48 typ es of audio interface format can be selected by th e tdm1 - 0 pins (bits), msn pin and dif1 - 0 pins (bits) ( table 8 , table 9 ) . in all formats the serial data is msb-first, 2's complement form at. in master mode , the sdto1 - 4 is clocked out on the falling edge of bick. normal output in slave mode , the sdto1 - 4 is clocked out on the falling edge of bick if 8 khz fs 216 khz. in other conditions, the data is clocked out on the prior rising edge of bick to compensate for some delay that renders the edge of data transition near bick falling edge. audio interface format is distinguished in four types: normal m ode, tdm128 mode, tdm256 mode and tdm512 mode are available. the tdm1 - 0 pins (bits) select these modes. in normal mod e (non tdm) , ain1 and ain2 a/d converted data is output from the sdto1 pin, ain3 and ain4 a/d converted data is output from the sdto2 pin , ain 5 and ain 6 a/d converted data is output from the sdto 3 pin, ain 7 and ain 8 a/d converted data is output from the sdto 4 pin. the bick frequency must be in the rage from 48fs to 128fs (fs= 48 khz) in slave mode if the audio interface format is in n ormal output ( non tdm ) and the interface speed is in normal, double or quad mode. bit length of a/d data is 24 - bit or 32 - bit and it is selected by the dif1 pin (bit). the bick frequency must be set to 32fs, 48fs or 64fs in slave mode if the audio interface for mat is normal output (non tdm) and the interface speed is in oct mode. bit length of a/d data is determined by bick frequency regardless of the dif1 pin (bit) if the bick frequency is 32fs or 48fs. it is 16 - bit when the bick frequency is 32fs and 24 - bit wh en the bick frequency is 48fs. when the bick frequency is 64fs, a/d data can be selected between 24 - bit and 32 - bit by the dif1 pin (bit). the bick frequency must be set to 32fs or 48fs in slave mode if the audio interface format is normal output (non tdm) and the interface speed is in ext mode. bit length of a/d data is determined by bick frequency regardless of the dif1 pin (bit). it is 16 - bit when the bick frequency is 32fs and 24 - bit when the bick frequency is 48fs.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 35 - the bick frequency will be 64fs in m aster mode if the audio interface format is normal output (non tdm) and the interface speed is normal, double or quad mode. data bit length can be selected from 24 - bit and 32 - bit by the dif1 pin (bit). the mclk frequency must be 64fs or 96fs in master mo de if the audio interface format is normal output (non tdm) and the interface speed is oct mode. the bick frequency will be 64fs. data bit length can be selected from 24 - bit and 32 - bit by the dif1 pin (bit). the bick frequency will be synchronized with th e mclk frequency in master mode if the audio interface format is normal output (non tdm) and the interface speed is hex mode. the mclk frequency must be 32fs, 48fs or 64fs. the bit length of a/d data is 16 - bit when the mclk frequen cy is 32fs, 24 - bit when t he mclk frequency is 48fs and 24 - bit or 32 - bit can be selected by the dif1 pin (bit) when the mclk frequency is 64fs. t h e dif0 pin selects the a/d data format between msb justified and i 2 s compatible. no. multiplex mode speed mode tdm1 pin(bit) tdm0 pin( bit) msn p in dif1 pin(bit) dif0 pin(bit) sdto lrck bick mclk pol. i/o freq. i/o freq. i/o 0 normal normal double quad l(0) l(0) l l(0) l(0) 24 - bit, msb h/l i 48 - 128fs i 128 - 1024fs i 1 l(0) h(1) 24 - bit, i 2 s l/h i 48 - 128fs i 128 - 1024fs i 2 h(1) l(0) 32 - bit, msb h/l i 64 - 128fs i 128 - 1024fs i 3 h(1) h(1) 32 - bit, i 2 s l/h i 64 - 128fs i 128 - 1024fs i 4 h l(0) l(0) 24 - bit, msb h/l o 64fs o 128 - 1024fs i 5 l(0) h(1) 24 - bit, i 2 s l/h o 64fs o 128 - 1024fs i 6 h(1) l(0) 32 - bit, msb h/l o 64fs o 128 - 1024fs i 7 h(1) h(1) 32 - bit, i 2 s l/h o 64fs o 128 - 1024fs i 8 oct hex l(0) l(0) l * l(0) 16 - bit, msb i 32fs i 32 - 96fs i 9 * h(1) 16 - bit, i 2 s i 32fs i 32 - 96fs i 10 * l(0) 24 - bit, msb i 48fs i 32 - 96fs i 11 * h(1) 24 - bit, i 2 s i 48fs i 32 - 96fs i 12 l(0) l(0) 24 - bit, msb i 64fs i 32 - 96fs i 13 l(0) h(1) 24 - bit, i 2 s i 64fs i 32 - 96fs i 14 h(1) l(0) 32 - bit, msb i 64fs i 32 - 96fs i 15 h(1) h(1) 32 - bit, i 2 s i 64fs i 32 - 96fs i 16 h * l(0) 16 - bit, msb o 32fs o 32fs i 17 * h(1) 16 - bit, i 2 s o 32fs o 32fs i 18 * l(0) 24 - bit, msb o 48fs o 48fs i 19 * h(1) 24 - bit, i 2 s o 48fs o 48fs i 20 l(0) l(0) 24 - bit, msb o 64fs o 64 - 96fs i 21 l(0) h(1) 24 - bit, i 2 s o 64fs o 64 - 96fs i 22 h(1) l(0) 32 - bit, msb o 64fs o 64 - 96fs i 23 h(1) h(1) 32 - bit, i 2 s o 64fs o 64 - 96fs i table 8 . audio interface format (norm al m ode)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 36 - no. multiplex mode speed mode tdm1 pin(bit) tdm0 pin( bit) msn pin dif1 pin(bit) dif0 pin(bit) sdto lrck bick mclk edg. i/o freq. i/o freq. i/o 24 tdm128 normal double quad l(0) h(1) l l(0) l(0) 24 - bit, msb i 128fs i 128 - 1024fs i 25 l(0) h(1) 24 - bit, i 2 s i 128fs i 128 - 1024fs i 26 h( 1) l(0) 32 - bit, msb i 128fs i 128 - 1024fs i 27 h(1) h(1) 32 - bit, i 2 s i 128fs i 128 - 1024fs i 28 h l(0) l(0) 24 - bit, msb o 128fs o 128 - 1024fs i 29 l(0) h(1) 24 - bit, i 2 s o 128fs o 128 - 1024fs i 30 h(1) l(0) 32 - bit, msb o 128fs o 128 - 1024fs i 31 h(1) h(1) 32 - bit, i 2 s o 128fs o 128 - 1024fs i 32 tdm256 normal double h(1) l(0) l l(0) l(0) 24 - bit, msb i 256fs i 256 - 1024fs i 33 l(0) h(1) 24 - bit, i 2 s i 256fs i 256 - 1024fs i 34 h(1) l(0) 32 - bit, msb i 256fs i 256 - 1024fs i 35 h(1) h(1) 32 - bit, i 2 s i 256fs i 256 - 1024fs i 36 h l(0) l(0) 24 - bit, msb o 256fs o 256 - 1024fs i 37 l(0) h(1) 24 - bit, i 2 s o 256fs o 256 - 1024fs i 38 h(1) l(0) 32 - bit, msb o 256fs o 256 - 1024fs i 39 h(1) h(1) 3 2 - bit, i 2 s o 256fs o 256 - 1024fs i 40 tdm512 normal h(1) h(1) l l(0) l(0) 24 - bit, msb i 512fs i 256 - 1024fs i 4 1 l(0) h(1) 24 - bit, i 2 s i 512fs i 256 - 1024fs i 4 2 h(1) l(0) 32 - bit, msb i 512fs i 256 - 1024fs i 4 3 h(1) h(1) 32 - bit, i 2 s i 512fs i 256 - 1024fs i 4 4 h l(0) l(0) 24 - bit, msb o 512fs o 512 - 1024fs i 4 5 l(0) h(1) 24 - bit, i 2 s o 512fs o 512 - 1024fs i 4 6 h(1) l(0) 32 - bit, msb o 512fs o 512 - 1024fs i 4 7 h(1) h(1) 32 - bit, i 2 s o 512fs o 512 - 1024fs i table 9 . audio interface format (tdm m ode)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 37 - cascade connection in tdm m ode the ak553 8 supports cascade connection in tdm mode . all a/d converted data of connected ak553 8 are output from the sdto1 pin of the last ak553 8 by cascade conne ction. when the odp pin = l , a cascade connection of two devices in tdm 512 mode is supported. figure 29 shows a connection example. when the odp pin = h , a cascade connection of two up to sixteen devices is av ailable. when using multiple devices in slave mode on cascade connection, internal operation timing of each device may differ for one mclk cycle depending on mclk and bick input timings. to prevent this timing difference, bick should be more than 10 ns from mclk as shown in table 10 . to realize this timing, bick divided by two should be input on a falling edge of mclk as shown in figure 54 when mclk=2xbick (normal speed 1024fs mode). when mclk=bick (normal speed 512fs mode), mclk and bick should be input in - phase as shown in figure 55 to satisfy the timing shown in table 10 figure 29 . cascade connection 48khz 512 fs 16 ch tdm 256 fs , 512fs or 1024fs gnd lrck ak 55 3 8 #1 bick tdmi n sdto 1 mclk lrck ak 5 5 3 8 #2 bick tdmi n sdto 1 mclk tdm 512 48khz 512fs 16ch tdm 256fs, 512fs or 1024fs gn d lrck ak5 5 3 8 #1 bick tdmin sdto1 mclk lrck a k55 3 8 #2 bick tdmin sdto1 mclk tdm 512 slave mode slave mode master mode slave mode
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 38 - figure 30 . mode 0/4 timing (normal output , normal/double/quad speed m ode, msb j ustified, 24 - bit) fi gure 31 . mode 1/5 timing (normal output , normal/double/quad speed m ode, i 2 s compatible, 24 - bit) figure 32 . mode 2/6 timing (normal output , normal/double/quad speed m ode, msb j u stified, 32 - bit) figure 33 . mode 3/7 timing (normal output , normal/double/quad speed m ode, i 2 s compatible, 32 - bit) lrck bick(64fs) sdto 1 - 4 0 1 2 11 12 13 23 2 4 31 0 1 2 11 12 13 23 24 31 0 23 1 22 23 22 13 12 11 31 ain1/3 /5/7 data 13 12 0 23 : msb, 0: lsb 11 1 1 0 ain2/4/6/8 data lrck bick(64fs) sdto 1 - 4 0 1 2 3 2 2 2 3 2 4 2 5 0 0 1 31 29 30 23 : msb, 0: lsb ain1/3 /5/7 data 0 2 3 22 23 24 2 5 31 29 30 1 1 23 23 22 2 1 0 ain2/4/6/8 data 22 2 lrck bick(64fs) sdto 1 - 4 0 1 2 11 12 13 20 21 31 0 1 2 12 13 14 24 25 31 0 31 1 30 3 1 30 22 20 19 31 ain1/3 /5/7 data 22 20 1 1 31 : msb, 0: lsb 1 0 19 1 2 0 12 11 1 ain 2 / 4 / 6 / 8 data lrck bick(64fs) sdto 1 - 4 0 1 2 3 23 24 25 26 0 0 1 31 29 30 3 1 30 31 : msb, 0: lsb ain1/3 /5/7 data 14 2 3 23 24 25 26 0 31 29 30 1 0 1 2 3 15 16 31 30 16 15 14 3 1 2 0 ain 2 / 4 / 6 / 8 data
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 39 - figure 34 . mode 8/16 timing ( n ormal output , oct/hex speed m ode, msb j ustified, 16 - bit) figure 35 . mode 9/17 timing ( normal output , oct/hex speed m ode, i 2 s compatible, 16 - bit) figure 36 . mode 10/18 timing ( normal output , oct/hex speed m ode, msb j ustified, 24 - bit) figure 37 . mode 11/19 timing ( normal output , oct/hex speed m ode, i 2 s compatible, 24 - bit) lrck (slave) bick ( 32 fs) sdto 1 - 4 (o) 14 9 ain1/3/5/7 data 16 bick 32 bick 6 1 0 14 9 ain2/4/6/8 data 16 bick 6 1 lrck (master) 14 15 8 7 0 15 8 7 0 15 lrck (slave) bick ( 32 fs) sdto 1 - 4 (o) 14 9 ain1/3/5/7 data 16 bick 32 bick 6 1 0 14 9 ain2/4/6/8 data 16 bick 6 1 lrck (master) 14 15 8 7 0 15 8 7 0 15 lrck (slav e) bick ( 48 fs) sdto1 - 4 (o) 22 13 ain1/3/5/7 data 24 bick 48 bick 10 1 0 22 13 ain2/4/6/8 data 24 bick 10 1 lrck (master) 22 23 12 11 0 23 12 11 0 23 lrck (slav e) bick ( 48 fs) sdto1 - 4 (o) 22 13 ain1/3/5/7 data 24 bick 48 bick 10 1 0 22 13 ain2/4/6/8 data 24 bick 10 1 lrck (master) 22 23 12 11 0 23 12 11 0 23
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 40 - figure 38 . mode 12/20 timing ( normal output , oct/hex speed m ode, msb j ustified, 24 - bit) figure 39 . mode 13/21 timing ( normal output , oct/hex speed m ode, i 2 s compatible, 24 - bit ) figure 40 . mode 14/22 timing ( normal output , oct/hex speed m ode, msb j ustified, 32 - bit) figure 41 . mode 15/23 timing ( normal output , oct/hex speed m ode, i 2 s compatible, 32 - bit) lrck (slave) bick ( 6 4 fs) sdto1 - 4 (o) 22 ain1/3/5/7 data 32 bick 64 bick 7 0 22 1 5 ain2/4/6/8 data 32 bick 7 0 lrck (master) 22 23 8 23 8 23 1 5 lrck (slave) bick ( 64 fs) sdto1 - 4 (o) 22 1 5 ain1/3/5/7 data 32 bick 64 bick 7 0 22 1 5 ain2/4/6/8 data 32 bick 7 0 lrck (master) 22 23 8 23 8 23 lrck (slav e) bick ( 64 fs) sdto1 - 4 (o) 30 17 ain1/3/5/7 data 32 bick 64 bick 1 4 1 0 30 1 7 ain2/4/6/8 data 32 bick 1 4 1 lrck (master) 30 31 16 15 0 31 1 6 1 5 0 31 lrck (slav e) bick ( 64 fs) sdto1 - 4 (o) 30 1 7 ain1/3/5/7 data 32 bick 64 bick 1 4 1 0 30 17 ain2/4/6/8 data 32 bick 1 4 1 lrck (master) 30 31 1 6 1 5 0 31 1 6 1 5 0 31
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 41 - figure 42 . mode 24/28 timing (tdm128 m ode, msb j ustified, 24 - bit) figure 43 . mode 25/29 timing (tdm128 m ode, i 2 s compatibl e) figure 44 . mode 26/30 timing (tdm128 m ode, msb j ustified) lrck (slave) bick (256fs) sdto1 (o) 22 0 data 1 32 bick 128 bick 22 0 data 2 32 bick 22 0 data 3 32 bick 22 0 data 4 32 bick lrck (master) 22 sdto 3 - 4 (o) 23 23 23 23 23 s dto2 (o) 22 0 data 5 32 bick 22 0 data 6 32 bick 22 0 data 7 32 bick 22 0 data 8 32 bick 22 23 23 23 23 23 lrck (slave) bick (256fs) sdto1 (o) 22 0 data 1 32 bick 128 bick 22 0 data 2 32 bick 22 0 data 3 32 bick 22 0 data 4 32 bick lrck (master) 22 sdto 3 - 4 (o) 23 23 23 23 23 s dto2 (o) 22 0 data 5 32 bick 22 0 data 6 32 bick 22 0 data 7 32 bick 22 0 data 8 32 bick 22 23 23 23 23 23 lrck (slave) bick (256fs) sdto1 (o) 30 1 data 1 32 bick 128 bick 30 1 data 2 32 bick 0 30 1 data 3 32 bick 30 1 data 4 32 bick lrck (master) 30 sdto 3 - 4 (o) 31 0 31 0 31 0 31 0 31 s dto2 (o) 30 1 data 1 32 bick 30 1 data 2 32 bick 0 30 1 data 3 32 bick 30 1 data 4 32 bick 30 31 0 31 0 31 0 31 0 31
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 42 - figure 45 . mode 27/31 timing (tdm128 m ode, i 2 s compatible) figure 46 . mode 32/36 timing (tdm256 m ode, msb j ustified, 24 - bit) figure 47 . mode 33/37 timing (tdm256 m ode, i 2 s compatible, 24 - bit) lrck (slave) bick (256fs) sdto1 (o) 30 1 data 1 32 bick 128 bick 30 1 data 2 32 bick 0 30 1 data 3 32 bick 30 1 data 4 32 bick lrck (master) 30 sdto 3 - 4 (o) 31 0 31 0 31 0 31 0 31 s dto2 (o) 30 1 data 5 32 bick 30 1 data 6 32 bick 0 30 1 data 7 32 bick 30 1 data 8 32 bick 30 31 0 31 0 31 0 31 0 31 lrck (slave) bick (256fs) sdto1 (o) 22 0 data 1 32 bick 256 bick 22 0 data 2 32 bick 22 22 0 data 3 32 bick 22 0 data 4 32 bick lrck (master) 22 0 data 5 32 bick 22 0 data 6 32 bick 22 0 data 7 32 bick 22 0 data 8 32 bick sdto2 - 4 (o) 23 23 23 23 23 23 23 23 23 lrck (slave) bick (256 fs) sdto1 (o) 22 0 data 1 32 bick 256 bick 22 0 data 2 32 bick 22 0 data 3 32 bick 22 0 data 4 32 bick lrck (master) 22 0 data 5 32 bick 22 0 data 6 32 bick 22 0 data 7 32 bick 22 0 data 8 32 bick sdto2 - 4 (o) 23 23 23 23 23 23 23 23 23
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 43 - figure 48 . mode 34/38 timing (tdm256 m ode, msb j ustified , 32 - bit ) figure 49 . mode 35/39 timing (tdm256 m ode, i 2 s compatible , 32 - bit ) figure 50 . mode 40/44 timing (tdm512 m ode, msb j ustified, 24 - bit) lrck (slave) bick (25 6fs) sdto1 (o) 30 1 data 1 32 bick 256 bick 30 1 data 2 32 bick 30 30 1 data 3 32 bick 30 1 data 4 32 bick lrck (master) 30 1 data 5 32 bick 30 1 data 6 32 bick 30 1 data 7 32 bick 30 1 data 8 32 bick sdto2 - 4 (o) 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 lrck (slave) bick (256 fs) sdto1 (o) 30 1 data 1 32 bick 256 bick 30 1 data 2 32 bick 0 30 1 data 3 32 bick 30 1 data 4 32 bick lrck (master) 30 1 data 5 32 bick 30 1 data 6 32 bick 30 1 data 7 32 bick 30 1 data 8 32 bick sdto2 - 4 (o) 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 lrck (slave) bick ( 512 fs) sdto1 (o) 22 0 # 2 da ta 1 32 bick 512 bick 33 0 # 2 data 2 32 bick 22 0 # 2 data 3 32 bick 22 0 # 2 data 4 32 bick lrck (master) tdmi n (i) (# 1 sdto1) 22 0 # 1 data 1 32 bick 22 0 # 1 data 2 32 bick 30 22 0 # 1 data 3 32 bick 22 0 # 1 data 4 32 bick 22 0 # 2 data 5 32 bick 22 0 # 2 data 6 32 bick 22 0 # 2 data 7 32 bick 22 0 # 2 data 8 32 bick sdto2 - 4 (o) 22 0 # 1 data 1 32 bick 22 0 # 1 data 2 32 bick 22 0 # 1 data 3 32 bick 22 0 # 1 data4 32 bick 22 0 #1 data 5 32 bick 22 0 #1 data 6 32 bick 22 0 #1 data 7 32 bick 22 0 #1 data 8 32 bick 22 0 # 1 data 5 32 bick 22 0 # 1 data 6 32 bick 22 0 # 1 data 7 32 bick 22 0 # 1 data 8 32 bick 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 31 22 23 23 23 23 23 23 23 23 23
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 44 - figure 51 . mode 41/45 timing (tdm512 m ode, i 2 s compatible, 24 - bit) figure 52 . mode 42/46 timing (tdm512 m ode, m sb j ustified, 32 - bit) figure 53 . mode 43/47 timing (tdm512 m ode, i 2 s compatible, 32 - bit) parameter symbol m in . t yp . m ax . unit mclk to bick bick to mclk ns ns table 10 . tdm m ode clock timing lrck (slave) bick ( 512 fs) sdto1 (o) 22 0 # 2 data 1 32 bick 512 bick 22 0 # 2 data 2 32 bick 22 0 # 2 data 3 32 bick 22 0 # 2 data 4 32 bick lrck (master) t dmi n (i) (# 1 sdto1) 22 0 # 1 data 1 32 bick 22 0 # 1 data 2 32 bick 22 0 # 1 data 3 32 bic k 22 0 # 1 data 4 32 bick 22 0 # 2 data 5 32 bick 22 0 # 2 data 6 32 bick 2 2 0 # 2 data 7 32 bick 22 0 # 2 data 8 32 bick sdto2 - 4 (o) 22 0 # 1 data 1 32 bick 22 0 # 1 data 2 32 bick 22 0 # 1 data 3 32 bick 22 0 # 1 data4 32 bick 22 0 #1 data 5 32 bick 22 0 #1 data 6 32 bick 22 0 #1 data 7 32 bick 22 0 # 1 data 8 32 bick 22 0 # 1 data 5 32 bick 22 0 # 1 data 6 32 bick 22 0 # 1 data 7 32 bick 22 0 # 1 data 8 32 bick 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 lrck (slave) bick ( 512 fs) sdto1 (o) 30 1 # 2 data 1 32 bick 512 bick 30 1 # 2 data 2 32 bick 30 1 # 2 data 3 32 bick 30 1 # 2 data 4 32 bick lrck (master) tdmi n (i) (# 1 sdto1) 30 1 # 1 data 1 32 bick 30 1 # 1 data 2 32 bick 30 30 1 # 1 data 3 32 bick 30 1 # 1 data 4 32 bick 30 1 # 2 data 5 32 bick 30 1 # 2 data 6 32 bick 30 1 # 2 data 7 32 bick 30 1 # 2 data 8 32 bick sdto2 - 4 (o) 30 1 # 1 data 1 32 bick 30 1 # 1 data 2 32 bick 30 1 # 1 data 3 32 bick 30 1 # 1 data4 32 bick 30 1 #1 data 5 32 bick 30 1 #1 data 6 32 bick 30 1 #1 data 7 32 bick 30 1 #1 data 8 32 bick 30 1 # 1 data 5 32 bick 30 1 # 1 data 6 32 bick 30 1 # 1 data 7 32 bick 30 1 # 1 data 8 32 bick 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 30 31 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 lrck (slave) bick ( 512 fs) sdto1 (o) 30 1 # 2 data 1 32 bick 512 bick 30 1 # 2 data 2 32 bick 30 1 # 2 data 3 32 bick 30 1 # 2 data 4 32 bick lrck (ma ster) tdmi n (i) (# 1 sdto1) 30 1 # 1 data 1 32 bick 30 1 # 1 data 2 32 bick 30 1 # 1 data 3 32 bick 30 1 # 1 data 4 32 bick 30 1 # 2 data 5 32 bick 30 1 # 2 data 6 32 bick 30 1 # 2 data 7 32 bick 30 1 # 2 data 8 32 bick sdto2 - 4 (o) 30 1 # 1 data 1 32 bick 30 1 # 1 data 2 32 bick 30 1 # 1 data 3 32 bick 30 1 # 1 data4 32 bick 30 1 #1 data 5 32 bick 30 1 #1 data 6 32 bick 30 1 #1 data 7 32 bick 30 1 #1 data 8 32 b ick 30 1 # 1 data 5 32 bick 30 1 # 1 data 6 32 bick 30 1 # 1 data 7 32 bick 30 1 # 1 data 8 32 bick 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 31 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 0
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 45 - figure 54 . audio in terface t iming (slave m ode, tdm m ode , mclk=2bick) figure 55 . audio interface timing (slave m ode, tdm m ode , mclk=bick) [ 2 ] dsd m ode dsd output is available only when the ak553 8 is in master m ode. the dclk frequency can be selected from 64fs, 128fs and 256fs by setting the dsdsel1 - 0 pins (bits) . t h e ak553 8 enters phase modulation mode by setting pmod pin = h or pmod bit = 1 . it does not support phase modulation mode when the dclk frequency is 256fs. dckb bit controls dclk polarity . figure 56 . dsd m ode timing mclk bick tmcb tbim vih vil vih vil mclk bick tmcb tbim vih vil vih vil dclk ( 64fs, 128 fs , 256fs ) dckb bit = 1 dclk ( 64fs, 128 fs , 256fs ) dckb bit = 0 dsd o l, dsd o r normal dsd o l,dsd o r phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 46 - channel summation ( pcm m ode, dsd m ode) channel summation function improves the dynamic range and s/n performance by averaging all a/d data of multiple - channel that the same signal is input. the ak 553 8 supports 8 - to - 4 mode , 8 - to - 2 mode, 8 - to - 1mode . 8 - to - 4 mode (2 - stereo m ode) improve the dynamic range and s/n for 3 db ( 2.5 db in dsd mode) by averaging two channels. 8 - to - 2 mode (stereo m ode) improve the dyn amic range and s/n for 6 db (5 db in dsd m ode) by averaging four channels. 8 - to - 1 mode (mono m ode) improve the dyn amic range and s/n for 9 db (7.5 db in dsd mode) by averaging eight channels. not - summation m ode ( 4 - stereo m ode) normal mode that does not execute summation is called as not - summat ion mode or 4 - stereo m ode. refer to the section ch power down & channel summation m ode for details. optimal data placement ( pcm m ode , dsd m ode ) assigned data to the sdto1 - 4 slot is controlled by t h e odp pin setting in parallel control mode. when t he odp pin = l , the data is output by fixed data placement mode. channel assignment of data slot is fixed regardless of enable/disenable of channel summation. for example, averaging data of two channels are output to both channel slots. when the odp pi n = h , the data is output by optimal data placement mode that is uses data slot more efficiently . in optimal data placement mode, there are no data redundant of channel summation, and the data is output in msb justified. therefore, the maximum number of connecting device in cascade connection will be increased. if the ak553 8 is set to 8 - to - 4 mode ( 2 - stereo mode), two de vices can be connected in tdm256 mode, four de vices can be connected in tdm512 mode. if the ak553 8 is set to 8 - to - 2 mode ( stereo mode), tw o devices can be connected in tdm128 mode, four de vices can be connected in tdm256 mode and eight devices can be connected in tdm 512 mode. if the ak553 8 is set to 8 - to - 1 mode (mono mode), four devices can be connected in tdm128 mode, eight devices can be c onnected in tdm256 mode and sixteen devices can be connected in tdm512 mode. in serial control mode, the data output is optimal data placement mode regardless of the odp pin setting. refer to ch power down & channel summation m ode for details.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 47 - ch power down & channel summation setting ( pcm m ode, dsd m ode ) [1] parallel control m ode the setting of the pw 2 - 0 pins and the odp pin control s the channel power - down and channel summation mode setting in parallel mode ( table 11 - table 16 ) . the pdn pin must be set to l when changing the odp pin and the pw 2 - 0 pins. the power consump tion of the device can be improved by setting unused channels to power - down state. in this c ase, the channel circuit that is powered down will be res e t . when the odp pin = l , the pw2 - 0 pins control channel power - down and 8 - to - 4 mode. in this mode, ain1 and ain2 channel data are summed digitally and output from the sdto1 (dsdo l 1 and dsdo r 1) by dividing into half amplitude. in the same manner, ain3 and ain4 channel data are summed digitally and output from the sdto2 (dsd ol 2 and dsd or 2) by dividing into half amplitude. ain 5 and ain 6 channel data are summed dig itally and output from the sdto 3 (dsd o l 3 and dsd or 3 ) by dividing into half amplitude. ain 7 and ain 8 channel data are summed dig itally and output from the sdto 4 (dsd ol 4 and dsd or 4 ) by dividing into half amplitude. pw2 pin pw1 pin pw0 pin power on/off ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 l l l off off off off off off off off l l h on on off off on on on on l h l off off on on on on on on l h h on on on on on on on on h l l o ff on on on on on on on h l h on on off off on on on on h h l off off on on on on on on h h h on on on on on on on o n table 11 . channel power on/off (parallel control m ode, odp pin= l ) pw2 pin pw1 pin pw0 pin data on slot slot 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 l l l all l ) when the odp pin = h , the ak553 8 becomes optimal data placement mode and data slots can be used efficiently. the pw2 - 0 pins control power down , 8 - to - 4 mode, 8 - to - 2 mode and 8 - to - 1 mode. in 8 - to - 4 mode , ain1 and ain2 channel data are summed digitally and output from the sdto1 (dsd ol 1) of the slot1 by dividing into half amplitude. in the same manner, ain3 and ain4 channel data are summed digitally and output from the sdto 1 (dsd or1 ) of the slot2 by dividing into half am plitude. ain 5 and ain 6 channel data are summed digitally and output from the sdto 2 (dsd ol 2 ) of the slot3 by dividing into half amplitude. ain 7 and ain 8 channel data are summed digitally and output from the sdto 2 (dsd or2 ) of the slot4 by dividing into half amplitude. in 8 - to - 2 mode , ain1 - ain 4 channel data are summed digitally and output from the sdto1 (dsd ol 1) of the slot1 by dividing into quarter amplitude. ain 5 C ain 8 channel data are summed digitally and output
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 48 - from the sdto1 (dsd or 1) of the slot2 by d ividing into quarter amplitude. in 8 - to - 1 mode, ain1 C ain 8 channel data are summed digitally and output from the sdto1 (dsd ol 1) of the slot1 by dividing into 1/8 amplitude . pw2 pin pw1 pin pw0 pin power on/off ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 l l l off off off off off off off off l l h on on on on on on on on l h l on on on on on on on on l h h on on on on on on on on h l l on on on on on on on on h l h on on on on on on on on h h l on on on on on on on on h h h on on on on on on on on table 13 . channel power on/off ( parallel control m ode, odp pin= h ) pw2 pin pw1 pin pw0 pin data on slot slot 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 l l l all h , normal output )
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 49 - pw2 pin pw1 pin pw0 pin data on slot slot 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 l l l all h , tdm128) pw2 pin pw1 pin pw0 pin data on slot slot 8 slot 7 slot 6 slot 5 slot 4 slot 3 sl ot 2 slot 1 l l l all h , tdm256 & tdm512)
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 50 - [2] serial control m ode in 3 - wire serial mode or i 2 c mode , pw1 - 8 bits control the power of ain1 - 8 channels independently. ainn channel is powered down when pwn bit = 0 (n=1 - 8 ) and ainn channel is in normal operation when pwn bit = 1. the power - down channel is reset status and outputs all 0 . the channel summation is controlled by mono1 and mono2 bits. rstn bit must be 0 when changing the setting of mono1, mono2 and pw1 - 8 bits. mono2 bit mono1 bit data on slot (normal output & dsd mode ) slot 8 slot7 slot6 slot 5 slot 4 slot 3 slot 2 slot 1 0 0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 0 1 all
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 51 - data slot configuration [1] pcm m ode figure 57 . slot assign in pcm m ode sdto1 pin slot 1 slot 3 slot 2 slot 4 slot 1 all slot 1 sdto1 pin tdm512 sdto2 pin lrck period = 1/fs slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 tdmin sdto3 pin slot 5 slot 7 slot 6 slot 8 sdto4 pin all
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 52 - [2] dsd m ode figure 58 . slot assign in dsd m ode dsdol1 pin slot 1 lrck p eriod = 1/fs slot 2 slot 3 slot 4 dsdor1 pin dsdol2 pin dsdor2 pin dsdol3 pin slot 5 slot 6 slot 7 slot 8 dsdor3 pin dsdol4 pin dsdor4 pin
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 53 - digital filter setting (pcm m ode) the ak553 8 has four types of digital filters and they can be selected by sd pin (bit) and slow pin (bit). the filter setting is not available in oct speed mode, hex speed mode and dsd mode. so the setting of the d igital filter is ignored. sd pin (bit) slow pin (bit) filter l (0) l (0) sharp r oll - off f ilter l (0) h (1) slow r oll - off f ilter h (1) l (0) short d elay sharp r oll - off f ilter h (1) h (1) short d elay slow r oll - off f ilter table 20 . digital filter setting digital hpf ( pcm m ode ) the ak553 8 has a digital high - pass filter for dc offset (include internal offset) cancelation . t h e digital high - pass filter is enabled by setting the hpfe pin (bit) = h (1) . the cut - off frequency of the high - pass filter is fixed 1.0 hz when fs= 48 khz (normal speed m ode), 96 khz (double speed m ode) or 192 khz (quad speed m ode) . the high - pass filter is not available in oct speed mode, hex speed mode and dsd mode. so that the setting of the hpfe pin is ignored. the high pass - filter setting should be changed when all channels are reset condition . overflow detection (pcm m ode, dsd m ode) [1] pcm m ode the ak553 8 has an overflow detect function for the analog input. the ovf pin outputs h if one of ain1 - 8 channels overflows (more than ? 0.3 dbfs). the ovf pin returns to l when analog input overf lows are resolved. the ovf output for overflowed analog input has the same group delay as the adc. [2] dsd m ode overflow detection ( error detection function ) the ovf pin outputs h if any channel s dsd modulators overflows. the ovf pin returns to l whe n overflows are resolved.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 54 - ldo t he voltage range of tvdd is from 1.7 v to 1.98 v or from 3.0 v to 3.6 v. set on/off of the ldo by the ldoe pin according to tvdd voltage ( table 21 ) . the internal ldo is switched on/off depending on tvdd vo ltage range. ldoe pdn ldo vdd18 pin additional voltage range to tvdd pin l l off external power input 1.7 - 1.98 v 1.7 - 1.98 v l h off external power input 1.7 - 1.98 v 1.7 - 1.98 v h l off pull ed down by 500 ? (ldoe pin = l) the internal ldo does not work properly when the tvdd voltage range is from 1.7 v to 1.98 v . set the ldoe pin to l to switch off the ldo. a 1.7 v - 1.98 v is supplied from the vdd18 pin for internal logic circuits. the voltage difference between tvdd and vdd18 must be 0.1 v or less. [2] tvdd=3.0 - 3.6 v, l do is on (ldoe pin = h) the internal ldo should be on when the tvdd voltage range is from 3.0 v to 3.6 v. it will be the power supply for the internal logic circuit. the vdd18 pin will be a connection terminal for a stabilization capacitor. it is not possible to supply the power to external circuits from the vdd18 pin. reset the ak553 8 must be reset upon power up or when changing the clock setting or clock frequency. it can be reset by the pdn pin or pw2 - 0 pins and rstn bit or pw 8 - 1 bits.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 55 - power up/ down sequence the ak553 8 enters power - down mode by setting the pd n pin to l . digital filters are reset at the same time. [1] pcm m ode in slave mode, internal power down signal (internal pdn) is released by inputting mclk, bick and lrck after setting the pdn pin to h . in master mode, the internal pdn is released by inputting mclk after setting the pdn pin to h . initialization cycle starts when the internal pdn is released. t he output data of sdto will be valid in 583 x 1/ fs after exiting power - down mode in slave mode, it will be valid in 578 x 1/ fs after exiting po wer - down mode in master mode. during initialization, the adc digital outputs of both channels are in 2 s complement format and forced to 0 . the adc outputs settle to data correspondent to the input signals af ter the end of initialization . this s ettling t akes app roximately the group delay time . figure 59 . power - up/down sequence example notes (1) the pdn pin should be held to l for more than 150 n s after avdd and tvdd are powered up. (2) a. ld oe pin = h , i2c p in = h and ps n pin = h (parallel mode): the internal ldo is powered up by releasing pdn pin to h. the internal pdn is released b y toggling mclk for 16384times. b. ldoe pin = h and psn pin = l (register mode): the internal ldo is powered up by rel easing pdn pin to h. the internal pdn is released by toggling internal oscillator clock for 16384 times (max. 10 ms). c. ldoe pin = l : the internal pdn is released in 1 ms (max.) after releasing pdn pin to h . during this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). therefore, referring the output of digital pins and data transmission with a device on the same 3 - wire serial/i 2 c bus as the ak553 8 should be avoided in this period to prevent system err ors. (3) initialization cycle is 583/fs in slav e mode and 578/fs in master mode. (4) the adc output data is 0 during initialization cycle and power - down mode. (5) the digital output corresponding to analog i nput has group delay (gd). pdn pin power power - down normal operation clock in mclk,lrck,bick adc in ( analog ) a d c out ( digital ) don t care 0 data gd ( 3 ) ( 5 ) gd ( 5 ) 0 data don t care internal state ( 4 ) ( 4 ) (1) i nternal pdn (2) vdd 18 pin initialize power - down idle noise idle noise
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 56 - internal pdn release sequence figure 60 . internal pdn release sequence
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 57 - [2] dsd m ode the internal pdn is released by inputting mclk after setting the pdn pin to h . figure 61 . dsd o peration t iming notes: (1) th e internal ldo is powered up by releasing pdn pin to h. the internal pdn is released by toggling internal oscillator clock for 16384 times (max. 10ms). the internal pdn is released in max. 1 ms after releasing pdn pin to h . register writings become ava ilable when the internal pdn changes to 1 . during this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). therefore, referring the output of digital pins and data transmission with a device on the same 3 - wir e serial/i 2 c bus as the ak553 8 should be avoided in this period to prevent system errors. (2) initialization operation will be completed in 583/fs. (3) dsd output pins output l ( - full scale data) during power down and initializing operation . dsd output pins outp ut full scale data during p hase m odulation mode, a reset sequence and a ch power down status. (4) the ovf pin outputs h when an excessive signal is input and overflow is detected at internal modulator. the ovf pin status will change after group delay period from the excessive input. (5) in the case above (4), the dsd output data will not be correct. (6) the ovf pin returns to l when the input signal settled to a normal state and overflow status of the internal modulator is resolved. the ovf pin status will change a fter group delay period from the normal input. p dn pin power - d own normal operation mclk in adc in ( analog ) dsd out ( dig ital ) don t care ( 3 ) l ( - full scale data) don t care internal state ( 4 ) (1) (2) initialize power - d own ovf - pin normal data abnormal data normal data l ( - full scale data) (6) (5) i nternal pdn
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 58 - operation mode control operation modes of the ak553 8 are set by pins or registers. in parallel control mode, the operation mode is set by pin and register settings are invalid. therefor the functions tha t needs register settings are not available in parallel control mode. for register accessing, 3 - wire serial and i 2 c bus communications are available. this control mode of the ak553 8 is selected by the i2c pin and the psn pin. in serial control mode, regist er settings are prioritized so that all pin settings except the msn pin setting are ignored. i2c pin ps n pin control m ode l l 3 - wire serial l h 3 - wire serial h l i 2 c bus h h parallel table 22 . control m ode register control interface (1) 3 - wire serial control m ode (i2c pin = l ) the internal registers may be written through the 3 - wire p interface pins (csn, cclk and cdti). the data on this interface consists of a 2 - bit chip address, read/write (1bit, fi xed to 1, write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after a low - to - h igh transition of csn. the clock speed of cclk is 5mhz (max). the internal registers are initialized by setting the pdn pin = l. in serial control mode, an internal timing circuit is reset by setting rstn bit = 0 but register values are not initialize d. c1 - c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 1 , write only) a4 - a0: register address d7 - d0: control data figure 62 . control i/f timing * the ak553 8 does not support read comman ds in 3 - wire serial control mode. * when the ak553 8 is in power down mode (pdn pin = l), a writing into the control registers is prohibited. * the control data cannot be written when the cclk rising edge is 15 times or less, or 17 times or more during cs n is l. cdti cclk c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 59 - (2) i 2 c - bus control m ode (i2c pin = h and psn pin = l) the ak553 8 supports the fast - mode i2c - bus (max: 400 khz, ver1.0). (2) - 1. write operations figure 63 shows the data transfer sequence of the i2c - bus control mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 69 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as 00100. the next bits are cad1 - 0 (device address bits). this bits identifies the specific de vice on the bus. the hard - wired input pins (cad1 - 0 pins) set these device address bit ( figure 64 ). if the slave address matches that of the ak553 8 , the ak553 8 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 70 ). r/w bit = 1 indicates that the read operation is to be executed. 0 in dicates that the write operation is to be executed. the second byte consists of the control register address of the ak553 8 . the format is msb first, and those most significant 3 - bits are fixed to zeros ( figure 65 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 66 ). the ak553 8 generates an acknowledge after each byte is received. data transfer is always terminated by a stop condit ion generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 69 ). the ak553 8 can perform more than one byte write operation per sequence. after receipt of t he third byte the ak553 8 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 6 - bit addr ess counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 07h prior to generating a stop condition, the address counter will roll over to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 71 ) except for the start a nd stop conditions. figure 63 . data transfer sequence at the i 2 c - bus control mode 0 0 1 0 0 cad1 cad0 r/w (cad0 and cad1 are set by pins) figure 64 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 65 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 66 . byte structure after the second byte 3rd byte 2nd byte 1st byte sda s t a r t a c k a c k s slave address a c k sub address(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= 0 a c k
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 60 - (2) - 2. read operations set the r/w bit = 1 for the read operation of the ak553 8 . after tran smission of data, the master can read the next addresss data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the internal 6 - bit address counter is incremented b y one, and the next data is automatically taken into the next address. if the address exceeds 07h prior to generating stop condition, the address counter will roll over to 00h and the data of 00h will be read out. the ak553 8 supports two basic rea d operations: current address read and random address read. (2) - 2 - 1. current address read the ak553 8 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a rea d or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit 1, the ak553 8 generates an acknowledge, transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak553 8 ceases transmission. figure 67 . curre nt address read (2) - 2 - 2. random address read the random read operation allows the master to access any memory location at random. prior to issuing a slave address with the r/w bit =1, the master must execute a dummy write operation first. the master i ssues a start request, a slave address (r/w bit = 0) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit =1. the ak553 8 then generat es an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak553 8 ceases transmission. figure 68 . random address read sda s t a r t a c k a c k s slave address a c k data(n+1) p s t o p data( n+x) a c k data(n+2) a c k r/w= 1 a c k data(n) sda s t a r t a c k a c k s slave address a c k data(n) p s t o p data( n+x) a c k data(n+1) a c k r/w= 0 a c k sub address(n) s t a r t a c k s slave address r/w= 1
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 61 - figure 69 . start and stop conditions figure 70 . acknowledge on the i 2 c - bus figure 71 . bit transfer on the i 2 c - bus scl sda stop condition start condition s p scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 scl sda data line stable; data valid change of data allowed
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 62 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 p w8 p w7 p w6 p w5 p w4 p w3 p w2 p w1 01h power management 2 0 0 0 0 0 mono2 mono1 rstn 02h control 1 0 cks3 cks2 cks1 cks0 dif1 dif0 hpfe 03h control 2 0 tdm1 tdm0 0 0 0 0 0 04h control 3 dp 0 0 0 0 0 sd slow 05h dsd 0 0 dcks 0 pmod dckb dsdsel1 dsdsel0 06h test1 tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 07h test2 0 0 0 0 0 0 0 trst note 24 . data mu st not be written into addresses from 0 6 h to 1fh. note 25 . the bits indicated as 0 must contain a 0 value. when rstn bit is set to 0, the internal digital filter and the control block are reset but the register values are n ot initialized. note 26 . when the pdn pin is set to l, all registers are initialized to their default values. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 p w8 p w7 p w6 p w5 p w4 p w3 p w2 p w 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 pw 8 - 1 : power down control for channel 8 - 1 0: p ower off 1: p ower on (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 0 0 0 0 mono2 mono1 rstn r/w r/w r/w r/w r /w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. all registers are not initialized. 1: normal operation (default) internal clock timings are reset but registers are not reset. mono2 - 1: channel summation m ode select ( table 17 , table 18 , table 19 ) 00: not - summation m ode (default) 01: 8 - to - 2 m ode 10: 8 - to - 4 m ode 11: 8 - to - 1 m ode
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 63 - addr re gister name d7 d6 d5 d4 d3 d2 d1 d0 02h control 1 0 cks3 cks2 cks1 cks0 dif1 dif0 hpfe r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 hpfe : high pass filter enable 0: high pass filter off 1: high pass filter on (default) when this bit is 1, digital hpfs for all channels are on. dif1 - 0: audio data interface m ode select ( table 8 , table 9 ) select a/d data bit length (24 - bit/32 - bit) and the format (msb justi fied/ i2s compatible) cks3 - 0: sampling speed mode and mclk frequency select ( table 5 ) select sampling speed and mclk frequency. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 3 h control 2 0 tdm1 tdm0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 tdm1 - 0: tdm modes select ( table 9 ) select the a/d data multiplex mode from normal, tdm128, tdm256 and tdm512 modes. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 4 h control 3 dp 0 0 0 0 0 sd slow r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 slow: slow roll - off filter select ( table 20 ) 0: sharp roll - off (default) 1: slow roll - off select roll - off ch aracteristic of the digital filter. sd: short delay select ( table 20 ) 0: normal delay (default) 1: short delay select group delay of the digital filter. dp : dsd mode select 0: pcm m ode (default) 1: dsd m ode selec t a/d data output mode.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 64 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 5 h dsd 0 0 dcks 0 pmod dckb dsdsel1 dsdsel0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dsdsel1 - 0 : select the f requency of dclk 00 : 64fs ( d efault) 01 : 128fs 10 : 256f s 11 : reserved dckb : polarity of dclk 0 : dsd data is output from dclk f alling e dge ( d efault) 1 : dsd data is output from dclk r ising e dge pmod : dsd phase modulation mode 0 : not phase modulation m ode ( d efault) 1 : phase modulation m ode dsd output phase mo dulation mode enable dcks: master clock frequency select at dsd m ode (dsd o nly) 0: 512fs (default) 1: 768fs addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h test1 tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 tst7 - 0 : test register. this register must be used as the default setting. normal operation is not guaranteed if all bits are not 0 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h test2 0 0 0 0 0 0 0 trst r/w r/w r/w r/w r/w r/w r/w r/w w default 0 0 0 0 0 0 0 0 trst: test register. this register must be 0 . this register must be 0. this register must be used as the default setting. normal operation is not guaranteed if all bits are not 0 .
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 65 - 13. recommended external circuits figure 72 shows recommended external connection. figure 72 . typical connection diagram note 27 . all digital input pins must not be allowed to float. msn pw2 pw1 pw0 pdn vdd18 dvss tvdd mclk test ain8p ain8n vrefl4 vrefh4 ain7n ain7p sd/pmod slow/dckb cks3/cad1 cks2/scl/cclk cks1/cad0_i2c/csn cks0/sda/cdti ovf dsdor4 dsdol4 sdto4/dsdor3 sdto3/dsdol3 sdto2/dsdor2 sdto1/dsdol2 tdmin/dsdor1 lrck/dsdol1 bick/dclk 1 avss1 avdd1 ain3p ain3n vrefl2 vrefh2 ain4n ain4p ain5p ain5n vrefh3 vrefl3 ain6n ain6p av dd2 avss2 dif0/ dsdsel0 dif1/dsdsel1 tdm0 tdm1 psn/cad0_spi i2c dp hpfe/dcks ldoe odp ain1p ain1n vrefl1 vrefh1 ain2n ain2p 2 3 4 5 6 7 8 9 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4.7 ? + 0.1 ? 10 ? + 0.1 ? 100 ? + 0.1 ? 100 ? 10 ? 0.1 ? 0.1 ? 0.1 ? 0.1 ? 100 ? 100 ? 10 ? + + + + digital 3.3v ain3+ ain3 ? ain4 ? ain4+ ain5+ ain5 ? ain6 ? ain6+ ain7 ? ain7+ ain8+ ain8 ? ain2+ ain2 ? ain1 ? ain1+ analog 3.3v analog 3.3v analog 3.3v mode setting mode setting mode setting controller controller mater clock fs 64fs AK5538 top view analog 3.3v 20 analog 3.3v 20 analog 3.3v 20 20 + 0.1 ?
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 66 - 1. grounding and power supply decoupling the ak553 8 requires careful attention to power supply and grounding arrangements. normally avdd 1/2 and tvdd are supplied from analog supply of the system. the power - up sequence between avdd 1/2 and tvdd are not critica l when avdd 1/2 and tvdd are supplied separately. dvss and avss 1/2 must be connected to the same analog ground plane. system analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are br ought onto the printed circuit board. decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. reference voltage the differential voltage between the vrefh1 - 4 pin s and the vrefl1 - 4 pi n s are the common voltage of a/d conversion. the vrefl1 - 4 pin s are normally connected to avss . in order to remove a high frequency noise, connect a 20 resistor between the vrefh1 - 4 pins and analog 3.3 v supply, and connect a 0.1 f ceramic capacitor in parallel with an 100 f ele ctrolytic capacitor between th e vrefh1 - 4 pin s and the v refl1 - 4 pin s . especially the ceramic capacitor should be connected as close as possible to the pin. all digital signals, especially clocks, should be kept away from the vrefh1 - 4 pins and vr efl1 - 4 pins in order to avoid unwanted noise couplin g into the ak553 8 . 3. analog inputs the analog input signal is differentially supplied into the modulator via the ainn+ and the ainn - pins (n= 1 - 8 ). the input voltage is the difference between the alinn+ and alinn - pins (n= 1 - 8 ). the full scale signal on each pin is nominally 1.85 v (typ). a voltage from avss1 /2 to avdd 1/2 can be input to the ak553 8 . the output code format is twos complement. the internal hpf removes dc offset (including dc offset by the adc itself ). the ak553 8 requires a + 3.3 v analog supply voltage. any voltage which exceeds the upper limit of avdd 1/2 +0.3 v and lower limit of avss 1/2 ? 0.3 v and any current beyond 10 ma for the analog input pins should be avoided. excessive currents to the input pi ns may damage the device. hence input pins must be protected from signals at or beyond these limits. use caution especially when using 15 v for other analog circuits in the system.
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 67 - 4. external analog circuit examples figure 73 shows an input buffer circuit example 1. (1 st order hpf; fc= 0.70 hz, 2 nd order lpf; fc= 351 khz, gain= ? 14.5 db). the analog signal is able to input through xlr or bnc connectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xl r input). the input level of this circuit is 9.85 vpp ( ak553 8 : 1.85 vpp typ.). when using this circuit, analog characteristics at fs= 48 khz is dr= 111 db, s/(n+d)= 103 db. the s/(n+d) characteristics of the ak553 8 varies depending on dc bias current of th e input signal. set the dc bias voltage in a range from 0.4 8 x avdd to 0.52 x avdd for a better characteristic. * film capacitors are recommended for the components shown as 15nf and 1 nf in the figure below. figure 73 . input buffer e xample1 fin 1hz 10hz frequency response ? ? ? 4.7k - + - + 1 0 3. 3k 620 - + 10 620 analog in 9.85 vpp 68 njm5534 va=+ 3.3 v vp= ? 15v 4.7k 10 + 1 0 k 10k 0.1 bias va+ 1.85 vpp 1.85 vpp vp+ vp - bias 1n * 3.3k 1n * bias 15 n * 68 xlr vin - vin + jp1 jp2 njm5534 njm5534 ak 55 3 8 a in n + ak5 5 3 8 a in n - 100p 100p
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 68 - 14. package outline dimensions 64 - pin qfn (unit mm) material & lead finish package molding compound: epoxy resin lead frame material: cu terminal surface treatment: solder (pb free) plate marking 1) pin #1 indication 2) date code : xx x xxxx ( 7 digits) 3) marketing code : ak553 8v n 4) akm logo akm ak553 8 vn xxxxxxx 1 b a c 0 . 6 0 m a x 0 . 8 5 + 0 . 1 5 - 0 . 0 5 0 . 0 2 + 0 . 0 3 - 0 . 0 2 0 . 2 0 0 . 25 + 0 . 05 - 0 . 07 0 . 50 9 . 00 0 . 15 8 . 75 9 . 0 0 0 . 1 5 8 . 7 5 6 . 1 5 6 . 15 0 . 40 0 . 10 0 . 10 m ab 1 16 17 32 33 48 49 64 48 49 33 32 17 16 64 1 s 0 . 08 s
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 69 - 15. ordering guide ak553 8v n ? 40 - 105 o c 64 - pin qfn akd 55 3 8 evaluation board for ak553 8 16. revision history date (y/m/d) revision reason page contents 1 6 / 03 / 1 6 00 first edition
[ ak553 8 ] 015099878 - e - 00 201 6/0 3 - 70 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm pro duct stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and appl ication examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of a km or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or thir d parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a mal function or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equ ipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in financ e - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or c orruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws a nd regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate t he inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with pro visions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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